The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be configured to provide quadrature filtering, complex filtering, 2-D convolution, 1-D/2-D correlations, and interpolating/decimating filters.
The FIR cells take advantage of symmetry in FIR coefficients by pre-adding data samples prior to multiplication. This allows an 8-tap FIR to be implemented using only 4 multipliers per filter cell. These cells can be configured as either a single 16-tap FIR filter or dual 8-tap FIR filters. Asymmetric filtering is also supported.
Decimation of up to 16 is provided to boost the effective number of filter taps from 2 to 16 times. Further, the Decimation Registers provide the delay necessary for fractional data conversion and 2-D filtering with kernels to 16x16.
The flexibility of the Dual is further enhanced by 32 sets of user programmable coefficients. Coefficient selection may be changed asynchronously from clock to clock. The ability to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering. The HSP43168 is a low power fully static design implemented in an advanced CMOS process. The configuration of the device is controlled through a standard microprocessor interface
| 芯片型号 | 产品状态 | 温度范围 | 封装尺寸图 | 潮湿敏感度等级MSL | 美元价格US $ |
| HSP43168JC-33 | 量产 | 民用级 | 84 Ld PLCC | 4 | 57.93 |
| HSP43168JC-33Z | 量产 | 民用级 | 84 Ld PLCC | 4 | 46.52 |
| HSP43168VC-45 | 量产 | 民用级 | 100 Ld MQFP | 4 | 79.49 |
| HSP43168VC-45Z | 量产 | 民用级 | 100 Ld MQFP | 3 | 58.45 |
| HSP43168JI-40 | 停产 | 工业级 | 84 Ld PLCC | 4 | N/A |
| HSP43168VC-33 | 停产 | 民用级 | 100 Ld MQFP | 4 | N/A |
| HSP43168VC-40 | 停产 | 民用级 | 100 Ld MQFP | 4 | N/A |