VIN (min) (V) | 5 |
VIN (max) (V) | 5 |
VOUT (min) (V) | 1.3 |
VOUT (max) (V) | 3.5 |
IOUT (max) (A) | 25 |
The HIP6018B provides the power control and protection for three output voltages in high-performance microprocessor and computer applications. The IC integrates a PWM controllers, a linear regulator and a linear controller as well as the monitoring and protection functions into a single package. The PWM controller regulates the microprocessor core voltage with a synchronous-rectified buck converter. The linear controller regulates power for the GTL bus and the linear regulator provides power for the clock driver circuit.
The HIP6018B includes an Intel-compatible, TTL 5-input digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 2.1VDC to 3.5VDC in 0.1V increments and from 1.3VDC to 2.05VDC in 0.05V steps. The precision reference and voltage-mode control provide ±1% static regulation. The linear regulator uses an internal pass device to provide 2.5V ±2.5%. The linear controller drives an external N-channel MOSFET to provide 1.5V ±2.5%.
The HIP6018B monitors all the output voltages. A single Power Good signal is issued when the core is within ±10% of the DAC setting and the other levels are above their under- voltage levels. Additional built-in over-voltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM over-current function monitors the output current by using the voltage drop across the upper MOSFET's rDS(ON), eliminating the need for a current sensing resistor.
芯片型号 | 产品状态 | 温度范围 | 封装尺寸图 | 潮湿敏感度等级MSL | 美元价格US $ |
HIP6018BCBZ | 量产 | 民用级 | 24 Ld SOIC | 3 | 2.64 |
HIP6018BCBZ-T | 量产 | 民用级 | 24 Ld SOIC T+R | 3 | 2.64 |
HIP6018BCB | 停产 | 民用级 | 24 Ld SOIC | 3 | N/A |
HIP6018BCBZA | 停产 | 民用级 | 24 Ld SOIC | 3 | N/A |
HIP6018BCBZA-T | 停产 | 民用级 | 24 Ld SOIC T+R | 3 | N/A |
HIP6018BEVAL1 | 停产 | 评估板 | N/A | N/A | |
HIP6018BCB-T | To Be Discontinued | 民用级 | 24 Ld SOIC T+R | 3 | 3.17 |