The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for channel selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latchup. DI also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see Application Note AN520).
The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic "1" and maximum 0.8V for logic "0". This allows direct interface without pullup resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200Ω resistor and diode clamp to each supply.
The HI-506 is a single 16-channel, the HI-507 is an 8-channel differential, the HI-508 is a single 8-channel and the HI-509 is a 4-channel differential multiplexer.
If input overvoltages are present, the HI-546/HI-547/HI-548/ HI-549 multiplexers are recommended.
| 芯片型号 | 产品状态 | 温度范围 | 封装尺寸图 | 潮湿敏感度等级MSL | 美元价格US $ |
| 77052012A | 量产 | 军用级 | 20 Ld LCC | N/A | 25.57 |
| HI1-0508-2 | 量产 | 军用级 | 20 Ld CerDIP | N/A | 6.84 |
| HI1-0508-5 | 量产 | 民用级 | 20 Ld CerDIP | N/A | 4.32 |
| HI3-0508-5 | 量产 | 民用级 | 16 Ld PDIP | N/A | 1.94 |
| HI3-0508-5Z | 量产 | 民用级 | 16 Ld PDIP | N/A | 1.62 |
| HI9P0508-5 | 量产 | 民用级 | 16 Ld SOIC | 1 | 2.08 |
| HI9P0508-5Z | 量产 | 民用级 | 16 Ld SOIC | 3 | 1.73 |
| HI9P0508-9 | 量产 | 工业级 | 16 Ld SOIC | 1 | 6.81 |
| HI9P0508-9Z | 量产 | 工业级 | 16 Ld SOIC | 3 | 5.68 |
| JM38510/19005BEA | 量产 | 军用级 | 20 Ld CerDIP | N/A | 75.98 |
| JM38510/19007BEA | 量产 | 军用级 | 20 Ld CerDIP | N/A | 30.16 |
| HI1-0508-4 | 停产 | 工业级 | 20 Ld CerDIP | N/A | N/A |
| HI4P0508-5 | 停产 | 民用级 | 20 Ld PLCC | N/A |