BBT3821LP-JH _ Intersil代理商WOSENDONGLI 代理BBT3821LP-JH

BBT3821LP-JH

The nLiten BBT3821 is a fully integrated octal 2.488Gbps to 3.1875Gbps Clock and Data Recovery (CDR) circuit and Retimer ideal for high bandwidth serial electrical or optical communications systems. It extracts timing information and data from serial inputs at 2.488Gbps to 3.1875Gbps, covering 10 Gigabit Fiber Channel (10GFC) and IEEE 802.3 specified 10 Gigabit Ethernet eXtended Attachment Unit Interface (XAUI) rates.

Each BBT3821 accepts two sets of four high-speed differential serial signals, re-times them with a local Reference Clock, reduces jitter, and delivers eight clean high-speed signals. The BBT3821 provides a full-function XAUI-to-10GBASE-CX4 PMA/PMD (compatible with the IEEE 802.3ak specification), and also can be configured to provide the electrical portion of a XAUI-to-10GBASE-LX4 PMA/PMD, needing only laser drivers and photo detectors to be added. In both these applications, the XAUI side can be configured to implement the XENPAK MSA_R3.0 specification, including full NVR and DOM support. The XPAK and X2 specifications currently all reference the XENPAK specification, and are supported in exactly the same manner. The BBT3821 can also be used to enhance a single full-duplex 10 Gigabit XAUI link, extending the driving distance of the high-speed (2.488Gbps to 3.1875Gbps) differential traces to 40 inches of FR4 PCB (assuming a proper impedance-controlled layout).

Each lane can operate independently with a data transfer rate of within ±100ppm of either 20x or 10x the local Reference Clock. The reference clock should be 156.25MHz for 10 Gigabit Ethernet XAUI applications, and 159.375MHz for 10 Gigabit Fiber Channel. Other reference frequencies can be used for proprietary rates. For other applications, each of the 8 lanes can be operated independently, within the same data rate and clock restrictions.

BBT3821LP-JH 特点

8 Lanes of Clock & Data Recovery and Retiming; 4 in Each Direction
Differential Input/Output
Wide Operating Data Rate Range: 2.488Gbps to 3.1875Gbps, and 1.244Gbps to 1.59325Gbps
Ultra Low-Power Operation (195mW typical per lane, 1550mW typical total consumption)
Low Power Version Available for LX4 Applications
17mm Square Low Profile 192 pin 1.0mm Pitch EBGA Package
Compliant to the IEEE 802.3 10GBASE-LX4(WWDM), 10GBASE-CX4, and XAUI Specifications
Reset Jitter Domain
Meets 802.3ae and 802.3ak Jitter Requirements with Significant Margin
Received Data Aligned to Local Reference Clock for Retransmission
Increase Driving Distance
LX4: Up to 40 inches of FR-4 Traces or 500 Meters of MMF Fiber at 3.1875Gbps
CX4: Over 15 meters of Compatible Cable
Deskewing and Lane-to-Lane Alignment
0.13mm Pure-Digital CMOS Technology
1.5V Core Supply, Control I/O 2.5V Tolerant
Clock Compensation
Tx/Rx Rate Matching via IDLE Insertion/Deletion up to ±100ppm Clock Difference
Receive Signal Detect and 16 Levels of Receiver Equalization for Media Compensation
CML CX4 Transmission Output with 16 Settable Levels of Pre-Emphasis, Eight on XAUI Side
Single-Ended or Differential Input Lower-Speed Reference Clock
Ease of Testing
Complete Suite of Ingress-Egress Loopbacks
Full 802.3ae Pattern Generation and Test, including CJPAT & CRPAT
PRBS (both 223-1 and 13458 byte) Built-In Self Tests, Error Flags and Count Output
JTAG and AC-JTAG Boundary Scan
Long Run Length (512 bit) Frequency Lock Ideal for Proprietary Encoding Schemes
Extensive Configuration and Status Reporting via 802.3 Clause 45 Compliant MDC/MDIO Serial Interface
Automatic Load of BBT3821 Control and all XENPAK Registers from EEPROM or DOM Circuit

BBT3821 芯片订购指南

芯片型号	产品状态	温度范围	封装尺寸图	潮湿敏感度等级MSL	美元价格US $
BBT3821-JH	量产	民用级	192 Ld BGA	3	33.68
BBT3821LP-JH	量产	民用级	192 Ld BGA	3	35.79

BBT3821LP-JH

BBT3821LP-JH 特点

BBT3821 芯片订购指南

BBT3821LP-JH 应用技术支持与电子电路设计开发资源下载