In normal operation, the BBT3420 transmitters accept data from the parallel data bus, clocked by the appropriate Transmit Byte Clock for the channel, and resynchronize it into the Transmit FIFO using the local reference clock. The data is then optionally encoded using the standard 8B/10B encoder, serialized, and sent out on the differential CML, XAUI-compatible transmit pins. The BBT3420 receivers accept serial data from the CML receive pins, perform clock and data recovery on the bit stream, scan the data for the Comma patterns, Byte-Aligns the data on either disparity of the sync pattern, and de-serializes the data. The data is then optionally 8B/10B decoded and fed into the receiver FIFO, where clock compensation, optional channel alignment, and resynchronization to any one of the individual recovered clocks, one channel clock, or the local reference clock are performed. In addition, several other features are provided to ease system testing. Loopback at either the serial or parallel ports is available under external pin or MDIO control. Suitable control and status registers are available through the IEEE standard MDIO/MDC system. The XGMII interface can be configured in source-centered or source synchronous timing formats for ASIC-friendly timing.
If the Built-in-Self-Test function (BIST) is in use, the serial transmit data is instead driven from a PRBS 223 -1 pattern generator. In the BIST mode, the received serial data is checked against the PRBS pattern transmitted and, if an error is found, a flag signal is provided.
| 芯片型号 | 产品状态 | 温度范围 | 封装尺寸图 | 潮湿敏感度等级MSL | 美元价格US $ |
| BBT3420-SN | 量产 | 民用级 | 289 Ld EBGA | 3 | 56.84 |
| BBT3420XP-EVAL | 量产 | 评估板 | N/A | 价格录入中 |