ATF1508BE-7AU100 CPLD可编程逻辑器件TQFP-100封装
| Commercial tpd |
5 ns, 7 ns |
| Generic Part |
1508 |
| I/O Pins |
100 |
| Macrocells |
128 |
| Power Options |
ULTRA-LOW |
| Registers |
128 |
| Usable Gates |
3000 |
| Vcc (V) |
1.8 |
| Pb-Free Packages |
TQFP 100 |
Ultra low power, Vcc-1.8V, 128 MC, ISP, High Speed CPLD in a Fully Green Package
The ATF1508BE is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 128 logic
macrocells and up to 84 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and
classic PLDs. The ATF1508BE’s enhanced routing switch matrices increase usable gate count
and the odds of successful pin-locked design modifications.
The ATF1508BE has up to 80 bi-directional I/O pins and four dedicated input pins. Each dedicated
input pin can also serve as a global control signal, register clock, register reset or output
enable. Each of these control signals can be selected for use individually within each macrocell.
Figures 1-1 and 1-2 show the pin assignments for the 100-lead TQFP and 132-ball CBGA packages,
respectively.
ATF1508BE-7AU100 特征
- High-density, High-performance Fully CMOS, Electrically-erasable Complex
Programmable Logic Device
– 128 Macrocells
– 5.0 ns Pin-to-pin Propagation Delay
– Registered Operation up to 333 MHz
– Enhanced Routing Resources
– Optimized for 1.8V Operation
– 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V
– SSTL2 and SSTL3 I/O Standards
- In-System Programming (ISP) Supported
– ISP Using IEEE 1532 (JTAG) Interface
– IEEE 1149.1 JTAG Boundary Scan Test
- Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– 5 Product Terms per Macrocell, Expandable up to 40
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate with Low Output Drive
– Programmable Open Collector Output Option
– Maximum Logic Utilization by Burying a Register with a Combinatorial Output and
Vice Versa
- Fully Green (RoHS Compliant)
- As Low As 10 μA Standby Current
- Power Saving Option During Operation Using PD1 and PD2 Pins
- Programmable Pin-keeper Option on Inputs and I/Os
- Programmable Schmitt Trigger Input Option on Input and I/O Pins
- Programmable Input and I/O Pull-up Option
- Unused I/O Pins Can Be Configured as Ground (Optional)
- Available in Commercial and Industrial Temperature Ranges
- Available in 100-lead TQFP and 132-ball CBGA
- Advanced Digital CMOS Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
- Security Fuse Feature
- Hot-Socketing Supported
ATF1508BE-7AU100 订货型号
ATF1508BE-7AU100 应用技术支持与电子电路设计开发资源下载
- ATMEL 爱特梅尔PLD可编程逻辑器件ATF1508BE 数据手册DataSheet 下载.PDF
- ATMEL 产品选型目录. PDF
- 相关SPLD / CPLD 可编程逻辑选型表
- Atmel CPLD Reference Designs . pdf(White Paper, 17 pages, updated 1/01)
This document describes three full applications using Logic Doubling techniques: 1) 8255 Serial IO expander with IO enable on every pin, 2) Low Power Serial IO expander and 32 LED driver, 3) Four 8-bit PWM generators, bus interface and value latches. Each fits in a 32 macrocell ATF1502 device. It also describes how to add transparent pin latch, ala HC573/373 into a corner of your CPLD. Click here for the Reference Design files for all these designs, plus a fourth Low Power Serial IO expander and 32 LCD driver application that uses each macrocell three ways and a Logic Doubling Tutorial.
- ATF15xx-DK2 CPLD 开发套件用户手册. pdf (User Guide, 47 pages, updated 8/02)
CPLD Development/Programmer Kit User Guide.
- ATF15xx 系列ISP 器件用户手册. pdf (User Guide, 54 pages, updated 7/01)
This document describes in detail the ATDH11xxPC series of ISP Board, Adapter Boards, Atmel's ATMISP software and Atmel's ISP download cable and gives detailed instructions for their use in programming Atmel's ATF15xx family of In-System Programmable CPLDs.
- ATF15xx 系列CPLD概述. pdf