ATF1504ASVL CPLD可编程逻辑器件

Commercial tpd	20
Generic Part .	1504
I/O Pins	44, 68, 84, 100
Macrocells	64
Registers	64
Usable Gates	1500
Vcc (V)	3.3
Packages	TQFP 100 PLCC 44 PLCC 68 PLCC 84 TQFP 44
Pb-Free Packages	TQFP 100 PLCC 44 PLCC 84 TQFP 44

Low Power,, Vcc-3.3V, 64 MC, ISP, Green package, CPLD

The ATF1504ASV(L) is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1504ASV(L) has up to 68 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 64 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1504ASV(L) allows fast, efficient generation of complex logic functions. The ATF1504ASV(L) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1504ASV(L) macrocell, shown in Figure 1, is flexible enough to support highlycomplex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs.

ATF1504ASVL 特征

• High-density, High-performance, Electrically-erasable Complex
• rogrammable Logic Device
  – 3.0 to 3.6V Operating Range
  – 64 Macrocells
  – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
  – 44, 68, 84, 100 Pins
  – 15 ns Maximum Pin-to-pin Delay
  – Registered Operation up to 77 MHz
  – Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell
  – D/T/Latch Configurable Flip-flops
  – Global and Individual Register Control Signals
  – Global and Individual Output Enable
  – Programmable Output Slew Rate
  – Programmable Output Open-collector Option
  – Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features
  – Automatic 5 μA Standby for “L” Version
  – Pin-controlled 100 μA Standby Mode (Typical)
  – Programmable Pin-keeper Circuits on Inputs and I/Os
  – Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
• Advanced EE Technology
  – 100% Tested
  – Completely Reprogrammable
  – 10,000 Program/Erase Cycles
  – 20 Year Data Retention
  – 2000V ESD Protection
  – 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• PCI-compliant
• Security Fuse Feature
• Green (Pb/Halide-free/RoHS Compliant) Package Options

ATF1504ASVL 订货型号

Devices	tPD (ns)	tCOS (ns)	fMAX (MHz)	Ordering Code	Package	Operation Range
ATF1504ASV	15	8	100	ATF1504ASV-15AU44 ATF1504ASV-15JU44 ATF1504ASV-15AU100	44A 44J 100A	Commercial (0°C to 70°C)
ATF1504ASVL	20	12	83.3	ATF1504ASVL-20AU44 ATF1504ASVL-20JU44 ATF1504ASVL-20AU100	44A 44J 100A	Industrial (-40°C to 85°C)

ATF1504ASVL 应用技术支持与电子电路设计开发资源下载

1. ATMEL 爱特梅尔PLD可编程逻辑器件ATF1504ASVL 数据手册DataSheet 下载.PDF
2. ATMEL 产品选型目录. PDF
3. 相关SPLD / CPLD 可编程逻辑选型表
4. Atmel CPLD Reference Designs . pdf(White Paper, 17 pages, updated 1/01)
   This document describes three full applications using Logic Doubling techniques: 1) 8255 Serial IO expander with IO enable on every pin, 2) Low Power Serial IO expander and 32 LED driver, 3) Four 8-bit PWM generators, bus interface and value latches. Each fits in a 32 macrocell ATF1502 device. It also describes how to add transparent pin latch, ala HC573/373 into a corner of your CPLD. Click here for the Reference Design files for all these designs, plus a fourth Low Power Serial IO expander and 32 LCD driver application that uses each macrocell three ways and a Logic Doubling Tutorial.
5. ATF15xx-DK2 CPLD 开发套件用户手册. pdf (User Guide, 47 pages, updated 8/02)
   CPLD Development/Programmer Kit User Guide.
6. ATF15xx 系列ISP 器件用户手册. pdf (User Guide, 54 pages, updated 7/01)
   This document describes in detail the ATDH11xxPC series of ISP Board, Adapter Boards, Atmel's ATMISP software and Atmel's ISP download cable and gives detailed instructions for their use in programming Atmel's ATF15xx family of In-System Programmable CPLDs.
7. ATF15xx 系列CPLD概述. pdf