ADN2804: 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
The ADN2804 provides the receiver functions of quantization, signal level detect, clock and data recovery, and data retiming for 622 Mbps NRZ data. The ADN2804 automatically locks to 622 Mbps data without the need for an external reference clock or programming. In the absence of input data, the output clock drifts no more than ±5%. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for -40°C to +85°C ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver.
The receiver’s front-end loss-of-signal (LOS) detector circuit indicates when the input signal level falls below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output.
The ADN2804 is available in a compact 5 mm × 5 mm, 32-lead LFCSP.
产品应用领域 Applications
- BPON ONT
- SONET OC-12
- WDM transponders
- Regenerators/repeaters
- Test equipment
- Broadband cross-connects and routers
ADN2804 特点
- Exceeds SONET requirements for jitter transfer/generation/tolerance
- Quantizer sensitivity: 3.3 mV typical
- Adjustable slice level: ±95 mV
- Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV
- Independent slice level adjust and LOS detector
- Patented clock recovery architecture
- No reference clock required
- Loss-of-lock indicator
- I^2C(R) interface to access optional features
- Single-supply operation: 3.3 V
- Low power: 423 mW typical
- 5 mm × 5 mm, 32-lead LFCSP, Pb free
ADN2804 功能框图
| 产品型号 | 产品状态 | 封装 | 引脚 | 温度范围 |
|---|---|---|---|---|
| ADN2804ACPZ | 量产 | 32 ld LFCSP (5x5mm CP-32-2) | 32 | 商业 |
| ADN2804ACPZ-500RL7 | 量产 | 32 ld LFCSP (5x5mm CP-32-2) | 32 | 商业 |
| ADN2804ACPZ-RL7 | 量产 | 32 ld LFCSP (5x5mm CP-32-2) | 32 | 商业 |
| EVAL-ADN2804EB | 量产 | 评估板 | - | 待定 |
| EVAL-ADN2804EBZ | 量产 | 评估板 | - | 待定 |