AD9516-0: 14-Output Clock Generator with Integrated 2.8 GHz VCO

The AD9516-0* provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz may be used.

The AD9516-0 emphasizes low jitter and phase noise to maximize data converter performance, and can benefit other applications with demanding phase noise and jitter requirements.

The AD9516-0 features six LVPECL outputs (in three pairs); four LVDS outputs (in two pairs); and eight CMOS outputs (two per LVDS output). The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.

The AD9516-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V.

The AD9516-0 is specified for operation over the industrial range of -40°C to +85°C.

产品应用领域 Applications

• Low jitter, low phase noise clock distribution
• Clocking high speed ADC, DAC, DDS, DDC, DUC, MxFE
• High performance wireless transceivers
• High performance instrumentation
• Broadband infrastructure
• ATE

AD9516-0 特点

• Eight 250 MHz CMOS outputs (two per LVDS output)
• Manual synchronization of outputs as needed

Low phase noise, phase-locked loop

• On-chip VCO tunes from 2.55 GHz to 2.95 GHz
• External VCO/VCXO to 2.4 GHz optional
• One differential or two single-ended reference inputs
• Reference monitoring capability
• Auto and manual reference switchover/holdover modes
• Autorecover from holdover
• Accepts references to 250 MHz
• Programmable delays in path to PFD
• Digital or analog lock detect, selectable
• 3 pairs of 1.6 GHz LVPECL outputs
  Each pair shares 1 to 32 divider with coarse phase delay
  Additive output jitter 225 fS rms
  Channel-to-channel skew paired outputs <10 ps
• 2 pairs of 800 MHz LVDS clock outputs
  Each pair shares two cascaded 1 to 32 dividers with coarse phase delay
  Additive output jitter 275 fS rms
  Fine delay adjust (ΔT) on each LVDS output
• Automatic synchronization of all outputs on power-up
• Serial control port
• 64-lead LFCSP

AD9516-0 功能框图

AD9516-0 芯片订购指南

产品型号	产品状态	封装	引脚	温度范围
AD9516-0/PCBZ	量产	None Available	64	工业
AD9516-0BCPZ	量产	64 ld LFCSP (9x9mm, 6.20mm exposed pad)	64	工业
AD9516-0BCPZ-REEL7	量产	64 ld LFCSP (9x9mm, 6.20mm exposed pad)	64	工业

AD9516-0 应用技术支持与电子电路设计开发资源下载

1. AD9516-0 数据手册DataSheet 下载 . PDF
2. ADI 模拟器件公司比较器产品选型指南 . PDF
3. Analog Devices, Inc. 美国模拟器件公司产品订购手册 .PDF
4. 时钟和定时IC产品介绍 . PDF