AD9511: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Three independent LVPECL and two LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz.
The PLL section consists of a programmable reference divider, R; a low-noise phase frequency detector, PFD; a precision charge pump, CP; and a programmable feedback divider, N. By connecting an external VCXO or VCO to the CLK2 and CLK2B pins, PLL output frequencies up to 1.6 GHz may be synchronized to the input reference, REFIN.
The clock distribution section provides LVPECL outputs and outputs that may be programmed to either LVDS or CMOS. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.
Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.
The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.
The AD9511 is available in a 48-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. Users wishing to extend the voltage range for external VCOs may run the charge pump supply, VCP, to 5.5V.
产品应用领域 Applications
- Low jitter, low phase noise clock distribution
- Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFETM Converters
- Wireless infrastructure transceivers
- High performance instrumentation
- Broadband infrastructure
AD9511 特点
- Phase locked loop (PLL) Core
Reference input frequencies to 250 MHz
Programmable dual-modulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCP) extends tuning range - Two 1.6 GHz, differential clock inputs
- 5 programmable dividers, 1 to 32, all integers
- Phase select for output-to-output coarse delay adjust
- Three independent 1.2 GHz LVPECL outputs
Additive output jitter , 225 fs RMS - Two independent 800 MHz/250 MHz LVDS/CMOS outputs
Additive output jitter, 275 fs RMS
Fine delay adjust on one output, 5-bit delay words - 4-wire or 3-wire serial control port
- Space-saving 48-lead LFCSP
AD9511 功能框图
| 产品型号 | 产品状态 | 封装 | 引脚 | 温度范围 |
|---|---|---|---|---|
| AD9511-VCO/PCB | 量产 | 评估板 | 48 | 商业 |
| AD9511/PCB | 量产 | 评估板 | 48 | 商业 |
| AD9511/PCBZ | 量产 | 评估板 | - | 商业 |
| AD9511BCPZ | 量产 | 48 ld LFCSP 7x7mm (5.25EP) | 48 | 工业 |
| AD9511BCPZ-REEL7 | 量产 | 48 ld LFCSP 7x7mm (5.25EP) | 48 | 工业 |
AD9511 应用技术支持与电子电路设计开发资源下载
- AD9511 数据手册DataSheet 下载 . PDF
- ADI 模拟器件公司比较器产品选型指南 . PDF
- Analog Devices, Inc. 美国模拟器件公司产品订购手册 .PDF
- 时钟和定时IC产品介绍 . PDF