| VSP01M02 | VSP2562 | VSP2582 | |
| Resolution(Bits) | 10 | 12 | 12 |
| Samples/Sec(MSPS) | 36 | 36 | 36 |
| Gain(Min)(dB) | -9 | -9 | -9 |
| Gain(Max)(dB) | 44 | 44 | 35 |
| Pd(Typ)(mW) | 139 | 86 | 85 |
| Supply Voltage(s)(V) | 2.7 - 3.6 | 2.7 - 3.3 | 2.7 - 3.3 |
| Output Data Format | CMOS Parallel | CMOS Parallel | CMOS Parallel |
| Pin/Package | 48LQFP | 36VQFN | |
| Operating Temperature Range(°C) | -25 to 85 | -25 to 85,-40 to 85 |
The VSP01M02 and VSP01M02 are complete mixed-signal ICs for charge-coupled device (CCD) signal processing with a built-in CCD timing generator, analog-to-digital converter (ADC), and CCD vertical driver. The AFE CCD channel has correlated double sampling to extract image information from the CCD output signal. Signal paths have gains ranging from -9 dB to +44 dB. The black level clamping circuit enables accurate black reference level and quick black level recovery after gain changes. An input signal clamp with CDS offset adjustment function is available. The system synchronizes the master clock, horizontal driver (HD), and vertical driver (VD). The VSP01M02 and VSP01M02 support all signal terminals required by CCD architecture.
| 器件 | 状态 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| VSP01M02ZWD | ACTIVE | 8.00 | 1ku | BGA (ZWD) | 100 | 360 | JEDEC TRAY (10+1) | VSP01M02 |
| VSP01M02ZWDR | ACTIVE | 7.25 | 1ku | BGA (ZWD) | 100 | 1000 | LARGE T&R | VSP01M02 |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| VSP01M02ZWD | Pb-Free (RoHS) | SNAGCU | Level-2-260C-1 YEAR | VSP01M02ZWD | |
| VSP01M02ZWDR | Pb-Free (RoHS) | SNAGCU | Level-2-260C-1 YEAR | VSP01M02ZWDR |