SN74LVT8996-EP 增强型产品 3.3V Abt 10 位多点可寻址 Ieee Std 1149.1 Tap 收发器

The 'LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETM devices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.

These devices are functionally equivalent to the 'ABT8996 ASPs. Additionally, they are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to interface to 5-V masters and/or targets.

Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP

SN74LVT8996-EP 特性

• Members of the Texas Instruments (TI TM) Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
• Extend Scan Access From Board Level to Higher Levels of System Integration
• Promote Reuse of Lower-Level (Chip/Board) Tests in System Environment
• While Powered at 3.3 V, Both the Primary and Secondary TAPs Are Fully 5-V Tolerant for Interfacing to 5-V and/or 3.3-V Masters and Targets
• Switch-Based Architecture Allows Direct Connect of Primary TAP to Secondary TAP
• Primary TAP Is Multidrop for Minimal Use of Backplane Wiring Channels
• Shadow Protocols Can Occur in Any of Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR TAP States to Provide for Board-to-Board Test and Built-In Self-Test
• Simple Addressing (Shadow) Protocol Is Received/Acknowledged on Primary TAP
• 10-Bit Address Space Provides for up to 1021 User-Specified Board Addresses
• Bypass ( BYP\) Pin Forces Primary-to-Secondary Connection Without Use of Shadow Protocols
• Connect ( CON\) Pin Provides Indication of Primary-to-Secondary Connection
• High-Drive Outputs (-32-mA IOH, 64-mA IOL) Support Backplane Interface at Primary and High Fanout at Secondary
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• Package Options Include Plastic Small-Outline (DW) and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic DIPs (JT)

SN74LVT8996-EP 应用技术支持与电子电路设计开发资源下载

1. SN74LVT8996-EP 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)