SN74ALVCH16601 具有三态输出的 18 位通用总线收发器
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCHR16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB.
| SN74ALVCH16601 | |
| Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
| Rating | Catalog |
| Technology Family | ALVC |
SN74ALVCH16601 特性
- Member of the Texas Instruments WidebusTM Family
- UBTTM Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes
- Operates From 1.65 V to 3.6 V
- Max tpd of 4.4 ns at 3.3 V
- ±12-mA Output Drive at 3.3 V
- Output Ports Have Equivalent 26-
Series Resistors, So No External Resistors Are Required
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
SN74ALVCH16601 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ALVCHR16601DLG4 | ACTIVE | -40 to 85 | 2.40 | 1ku | SSOP (DL) | 56 | 20 | TUBE | |
| 74ALVCHR16601GRE4 | ACTIVE | -40 to 85 | 1.85 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| 74ALVCHR16601GRG4 | ACTIVE | -40 to 85 | 1.85 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| 74ALVCHR16601LRG4 | ACTIVE | -40 to 85 | 2.05 | 1ku | SSOP (DL) | 56 | 1000 | LARGE T&R | |
| 74ALVCHR16601VRE4 | ACTIVE | -40 to 85 | 1.85 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R | |
| 74ALVCHR16601VRG4 | ACTIVE | -40 to 85 | 1.85 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R | |
| SN74ALVCHR16601DL | ACTIVE | -40 to 85 | 2.40 | 1ku | SSOP (DL) | 56 | 20 | TUBE | |
| SN74ALVCHR16601GR | ACTIVE | -40 to 85 | 1.85 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| SN74ALVCHR16601LR | ACTIVE | -40 to 85 | 2.05 | 1ku | SSOP (DL) | 56 | 1000 | LARGE T&R | |
| SN74ALVCHR16601VR | ACTIVE | -40 to 85 | 1.85 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R |
SN74ALVCH16601 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ALVCHR16601DLG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCHR16601DLG4 | 74ALVCHR16601DLG4 |
| 74ALVCHR16601GRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCHR16601GRE4 | 74ALVCHR16601GRE4 |
| 74ALVCHR16601GRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCHR16601GRG4 | 74ALVCHR16601GRG4 |
| 74ALVCHR16601LRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCHR16601LRG4 | 74ALVCHR16601LRG4 |
| 74ALVCHR16601VRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCHR16601VRE4 | 74ALVCHR16601VRE4 |
| 74ALVCHR16601VRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCHR16601VRG4 | 74ALVCHR16601VRG4 |
| SN74ALVCHR16601DL | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCHR16601DL | SN74ALVCHR16601DL |
| SN74ALVCHR16601GR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCHR16601GR | SN74ALVCHR16601GR |
| SN74ALVCHR16601LR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCHR16601LR | SN74ALVCHR16601LR |
| SN74ALVCHR16601VR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCHR16601VR | SN74ALVCHR16601VR |
SN74ALVCH16601 应用技术支持与电子电路设计开发资源下载
- SN74ALVCH16601 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)