SN65MLVD040 半双工 M-LVDS 收发器
The SN65MLVD200A/202A/204A/205A are multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30 
, and incorporates controlled transition times to allow for stubs off of the backbone transmission line.
These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of –1 V to 3
| SN65MLVD040 | |
| No. of Rx | 4 |
| No. of Tx | 4 |
| Input Signal | LVTTL, M-LVDS |
| Output Signal | M-LVDS, TTL |
| Signaling Rate(Mbps) | 250 |
| Supply Voltage(s)(V) | 3.3 |
| ICC(Max)(mA) | 90 |
| Receiver Type | 1 & 2 |
| Part-to-Part Skew(Max)(ps) | 600 |
| Rx tpd(Typ)(ns) | 6 |
| Tx tpd(Typ)(ns) | 2.4 |
| Pin/Package | 48VQFN |
| Operating Temperature Range(C) | -40 to 85 |
| ESD HBM(kV) | 8 |
SN65MLVD040 特性
- Low-Voltage Differential 30- to 55- Line Drivers and Receivers for Signaling Rates(1) Up to 250 Mbps; Clock Frequencies Up to
125 MHz
- Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
- Controlled Driver Output Voltage Transition Times for Improved Signal Quality
- –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
- Bus Pins High Impedance When Driver Disabled or VCC ≤ 1.5 V
- Independent Enables for each Driver and Receiver
- Enhanced ESD Protection: 7 kV HBM on all Pins
- 48 pin 7 X 7 QFN (RGZ)
- M-LVDS Bus Power Up/Down Glitch Free
- APPLICATIONS
- Parallel Multipoint Data and Clock Transmission Via Backplanes and Cables
- Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485
- Cellular Base Stations
- Central-Office Switches
- Network Switches and Routers
SN65MLVD040 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN65MLVD040RGZR | ACTIVE | -40 to 85 | 3.60 | 1ku | VQFN (RGZ) | 48 | 2500 | LARGE T&R | |
| SN65MLVD040RGZT | ACTIVE | -40 to 85 | 4.15 | 1ku | VQFN (RGZ) | 48 | 250 | SMALL T&R |
SN65MLVD040 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN65MLVD040RGZR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-3-260C-168 HR | SN65MLVD040RGZR | SN65MLVD040RGZR |
| SN65MLVD040RGZT | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-3-260C-168 HR | SN65MLVD040RGZT | SN65MLVD040RGZT |
SN65MLVD040 应用技术支持与电子电路设计开发资源下载
- SN65MLVD040 数据资料 dataSheet 下载.PDF
- TI 德州仪器M-LVDS PHYs选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)