SN65LVDM176 半双工 LVDM 收发器
The SN65LVDM176 is a differential line driver and receiver configured as a transceiver that uses low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbit/s. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50-
load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of less than 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.
The intended application of this device and signaling technique is for half-duplex or multiplex baseband data transmission over controlled impedance media of approximately 100- characteristic impedance
| SN65LVDM050 | |
| No. of Rx | 1 |
| No. of Tx | 1 |
| Input Signal | LVDM, LVTTL |
| Output Signal | LVDM, LVTTL |
| Signaling Rate(Mbps) | 400 |
| Supply Voltage(s)(V) | 3.3 |
| ICC(Max)(mA) | 15 |
| Part-to-Part Skew(Max)(ps) | 1000 |
| Rx tpd(Typ)(ns) | 3.7 |
| Tx tpd(Typ)(ns) | 1.7 |
| Pin/Package | 8MSOP, 8SOIC |
| Operating Temperature Range(C) | -40 to 85 |
| ESD HBM(kV) | 15 |
SN65LVDM176 特性
- Low-Voltage Differential Driver and Receiver for Half-Duplex Operation
- Designed for Signaling Rates of 400 Mbit/s
- ESD Protection Exceeds 15 kV on Bus Pins
- Operates From a Single 3.3-V Supply
- Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 50- Load
- Valid Output With as Little as 50 mV Input Voltage Difference
- Propagation Delay Times
- Driver: 1.7 ns Typ
- Receiver: 3.7 ns Typ
- Power Dissipation at 200 MHz
- Driver: 50 mW Typical
- Receiver: 60 mW Typical
- LVTTL Levels Are 5-V Tolerant
- Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V
- Open-Circuit Fail-Safe Receiver
- Surface-Mount Packaging
- D Package (SOIC)
- DGK Package (MSOP)
SN65LVDM176 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN65LVDM176D | ACTIVE | -40 to 85 | 1.80 | 1ku | SOIC (D) | 16 | 75 | TUBE | |
| SN65LVDM176DG4 | ACTIVE | -40 to 85 | 1.80 | 1ku | SOIC (D) | 16 | 75 | TUBE | |
| SN65LVDM176DR | ACTIVE | -40 to 85 | 1.50 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN65LVDM176DRG4 | ACTIVE | -40 to 85 | 1.50 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R |
SN65LVDM176 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN65LVDM176D | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDM176D | SN65LVDM176D |
| SN65LVDM176DG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDM176DG4 | SN65LVDM176DG4 |
| SN65LVDM176DR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDM176DR | SN65LVDM176DR |
| SN65LVDM176DRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDM176DRG4 | SN65LVDM176DRG4 |
SN65LVDM176 应用技术支持与电子电路设计开发资源下载
- SN65LVDM176 数据资料 dataSheet 下载.PDF
- TI 德州仪器M-LVDS PHYs选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)