OMAP3503 应用处理器

	OMAP3503
CPU	ARM Cortex-A8
RISC Frequency(MHz)	600
On-Chip L1/SRAM	32 KB (ARM Cortex-A8)
RAM	64 KB
On-Chip L2/SRAM	256 KB (ARM Cortex-A8)
ROM	32 KB (ARM Cortex-A8)
EMIF	1 32-Bit SDRC,1 16-Bit GPMC
External Memory Type Supported	LPDDR,NOR Flash,NAND flash,OneNAND,Asynch SRAM
DMA	64-Ch EDMA,32-Bit Channel SDMA
Video Port (Configurable)	1 Dedicated Output,1 Dedicated Input
MMC/SD	3
McBSP	5
Pin/Package	423FCBGA,515POP-FCBGA
POP Interface	Yes (CBB)
I2C	3
McSPI	4
HDQ/1-Wire	1
UART	3
USB	1 USB 2.0 HS 3-Port,1 USB 2.0 HS OTG
Timers	12 32-Bit GP,2 32-Bit WD
Core Supply (Volts)	0.8 V to 1.35 V
IO Supply (Volts)	1.8 V,3.0 V (MMC1 Only)
Operating Temperature Range (°C)	0 to 90,-40 to 105

特性

• OMAP3515/03 Applications Processor:
  • OMAP™ 3 Architecture
  • MPU Subsystem
    • 600-MHz ARM Cortex™-A8 Core
    • NEON™ SIMD Coprocessor
  • POWERVR SGX™ Graphics Accelerator (OMAP3515 Device Only)
    • Tile Based Architecture delivering 10 MPoly/sec
    • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
    • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
    • Fine Grained Task Switching, Load Balancing, and Power Management
    • Programmable High Quality Image Anti-Aliasing
  • Fully Software-Compatible With ARM9™
  • Commercial and Exteneded Temperature Grades
• ARM Cortex™-A8 Core
  • ARMv7 Architecture
    • Trust Zone®
    • Thumb®-2
    • MMU Enhancements
  • In-Order, Dual-Issue, Superscalar Microprocessor Core
  • NEON™ Multimedia Architecture
  • Over 2x Performance of ARMv6 SIMD
  • Supports Both Integer and Floating Point SIMD
  • Jazelle® RCT Execution Environment Architecture
  • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
  • Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug
• ARM Cortex™-A8 Memory Architecture:
  • 16K-Byte Instruction Cache (4-Way Set-Associative)
  • 16K-Byte Data Cache (4-Way Set-Associative)
  • 256K-Byte L2 Cache
• 112K-Byte ROM
• 64K-Byte Shared SRAM
• Endianess:
  • ARM Instructions - Little Endian
  • ARM Data — Configurable
• External Memory Interfaces:
  • SDRAM Controller (SDRC)
    • 16, 32-bit Memory Controller With 1G-Byte Total Address Space
    • Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
    • SDRAM Memory Scheduler (SMS) and Rotation Engine
  • General Purpose Memory Controller (GPMC)
    • 16-bit Wide Multiplexed Address/Data Bus
    • Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin
    • Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM
    • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.)
    • Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space)
• System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority)
• Camera Image Signal Processing (ISP)
  • CCD and CMOS Imager Interface
  • Memory Data Input
  • RAW Data Interface
  • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  • A-Law Compression and Decompression
  • Preview Engine for Real-Time Image Processing
  • Glueless Interface to Common Video Decoders
  • Histogram Module/Auto-Exposure, Auto-White Balance, and Auto-Focus Engine
  • Resize Engine
    • Resize Images From 1/4x to 4x
    • Separate horizontal/Vertical Control
• Display Subsystem
  • Parallel Digital Output
    • Up to 24-Bit RGB
    • HD Maximum Resolution
    • Supports Up to 2 LCD Panels
    • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
  • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
    • Composite NTSC/PAL Video
    • Luma/Chroma Separate Video (S-Video)
  • Rotation 90-, 180-, and 270-degrees
  • Resize Images From 1/4x to 8x
  • Color Space Converter
  • 8-bit Alpha Blending
• Serial Communication
  • 5 Multichannel Buffered Serial Ports (McBSPs)
    • 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5)
    • 5K-Byte Transmit/Receive Buffer (McBSP2)
    • SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations
    • Direct Interface to I2S and PCM Device and TDM Buses
    • 128 Channel Transmit/Receive Mode
  • Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports
  • High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface)
  • High-Speed/Full-Speed/Low-Speed Multiport USB Host Controller
    • 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface
    • Supports Transceiverless Link Logic (TLL)
  • One HDQ/1-Wire Interface
  • Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
  • Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
• Removable Media Interfaces:
  • Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO)
• Comprehensive Power, Reset, and Clock Management
  • SmartReflex™ Technology
  • Dynamic Voltage and Frequency Scaling (DVFS)
• Test Interfaces
  • IEEE-1149.1 (JTAG) Boundary-Scan Compatible
  • Embedded Trace Macro Interface (ETM)
  • Serial Data Transport Interface (SDTI)
• 12 32-bit General Purpose Timers
• 2 32-bit Watchdog Timers
• 1 32-bit 32-kHz Sync Timer
• Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
• 65-nm CMOS Technology
• Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
• Descreet Memory Interface (Not Available in CBC Package)
• Packages:
  • 515-pin s-PBGA Package (CBB Suffix), .5mm Ball Pitch (Top), .4mm Ball Pitch (Bottom)
  • 515-pin s-PBGA Package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch (Bottom)
  • 423-pin s-PBGA Package (CUS Suffix), .65mm Ball Pitch
• 1.8-V I/O and 3.0-V (MMC1 only), 0.975-V to 1.35-V Adaptive Processor Core Voltage, 0.975-V to 1.35-V Adaptive Core Logic Voltage
• Applications:
  • Portable Navigation Devices
  • Portable Media Player
  • Advanced Portable consumer Electronics
  • Digital TV
  • Digital Video Camera
  • Portable Data Collection
  • Point-of-Sale Devices
  • Gaming
  • Web Tablet
  • Smart White Goods
  • Ultra Mobile Devices

说明

OMAP3515 and OMAP3503 high-performance, applications processors are based on the enhanced OMAP™ 3 architecture. The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

• Streaming video
• 2D/3D mobile gaming
• Video conferencing
• High-resolution still image
• Video capture in 2.5G wireless terminals, 3G wireless terminals, and rich multimedia-featured handsets, and high-performance personal digital assistants (PDAs).

The device supports high-level operating systems (OSs), such as:

• Windows CE
• Symbian OS
• Linux
• Palm OS

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

• Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor
• SGX530 subsystem for 2D and 3D graphics acceleration to support display and gaming effects (3515 only)
• Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
• Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out.
• Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

• A comprehensive power and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex™ adaptative voltage control. This power management technique for automatic control of the operating voltage of a module reduces the active power consumption.
• Memory stacking feature using the package-on-package (POP) implementation (CBB package only)

OMAP3515/03 devices are available in a 515-pin PBGA package (CBB suffix) and a 423-pin PBGA package (CUS suffix). Some features of the CBB package are not available in the CUS package.

OMAP3503 应用处理器技术支持

• ARM微控制器选型手册（ Excel 文档格式）
• TMS470 微控制器选型手册（ PDF 文档格式）
• OMAP3515/ OMAP3503 数据手册DataSheet下载. pdf