CD40105B CMOS 4 位 x 16 字 FIFO 寄存器
CD40105B is a low-power first-in-first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems.
Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position's data is filed and a "0" denotes a vacancy in that positiion. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0
|
SN74V215 |
| Voltage Nodes(V) |
5, 10, 15 |
| Rating |
Military |
| Technology Family |
CD4000 |
CD40105B 特性
- Independent asynchronous inputs and outputs
- 3-state outputs
- Expandable in either direction
- Status indicators on input and output
- Reset capability
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package-temperature range): 1V at VDD = 5V, 2V at VDD = 10 V, 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications
- Bit rate smoothing
- CPU/terminal buffering
- Data communications
- Peripheral buffering
- Line printer input buffers
- Auto dialers
- CRT buffer memories
- Radar data acquisition
CD40105B 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD40105BE |
ACTIVE |
-55 to 125 |
1.20 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
| CD40105BEE4 |
ACTIVE |
-55 to 125 |
1.20 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
| CD40105BF3AS2283 |
OBSOLETE |
|
|
CDIP (J) | 16 |
|
|
CD40105B 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD40105BE |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD40105BE |
CD40105BE |
| CD40105BEE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD40105BEE4 |
CD40105BEE4 |
CD40105B 应用技术支持与电子电路设计开发资源下载
- CD40105B 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)