| ADS8364 | ADS8365 | |
| Resolution(Bits) | 16 | 16 |
| Sample Rate (max) | 250kSPS | 250kSPS |
| Architecture | SAR | SAR |
| Power Consumption(Typ)(mW) | 413 | 190 |
| SINAD(dB) | 82.5 | 87 |
| SNR(dB) | 83.2 | 88 |
| SFDR(dB) | 93.5 | 95 |
| DNL(Max)(+/-LSB) | 1.5 | 1.5 |
| INL(Max)(+/-LSB) | 8 | 4 |
| No Missing Codes(Bits) | 14 | 14 |
| ENOB(Bits) | 13.41 | 14.16 |
| No. of Supplies | 2 | 2 |
| Analog Voltage AV/DD(Min)(V) | 4.75 | 4.75 |
| Analog Voltage AV/DD(Max)(V) | 5.25 | 5.25 |
| Logic Voltage DV/DD(Min)(V) | 2.7 | 2.7 |
| Logic Voltage DV/DD(Max)(V) | 5.5 | 5.5 |
| Input Configuration Range | +/-2.5V at +2.5V | +/-2.5V at +2.5V |
| Reference Mode | Int and Ext | Int and Ext |
| Rating | Catalog | Catalog |
| Pin/Package | 64TQFP | 64TQFP |
| Comments | 250 kSPS per channel | 250 kSPS per channel |
| # Input Channels | 6 | 6 |
| Operating Temp Range(Celsius) | -40 to 85 | -40 to 85 |
The ADS8364 includes six, 16-bit, 250kSPS analog-to-digital converters (ADCs) with six fully differential input channels grouped into three pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC. This architecture provides excellent common-mode rejection of 80dB at 50kHz, which is important in high-noise environments.
The ADS8364 offers a flexible, high-speed parallel interface with a direct address mode, a cycle, and a FIFO mode. The output data for each channel is available as a 16-bit word.
| 器件 | 状态 | 温度(oC) | 价格（美元） | 封装 | 引脚 |
| ADS8364Y/250 | ACTIVE | -40 to 85 | 19.10 | 1ku | TQFP (PAG) | 64 |
| ADS8364Y/250G4 | ACTIVE | -40 to 85 | 19.10 | 1ku | TQFP (PAG) | 64 |
| ADS8364Y/2K | ACTIVE | -40 to 85 | 18.10 | 1ku | TQFP (PAG) | 64 |
| ADS8364Y/2KG4 | ACTIVE | -40 to 85 | 18.10 | 1ku | TQFP (PAG) | 64 |