ADS61B23 具有缓冲差动输入的 12 位 80MSPS ADC

	ADS61B23
Resolution(Bits)	12
Sample Rate (max)	80MSPS
Architecture	Pipeline
Power Consumption(Typ)(mW)	351
SINAD(dB)	69.7
SNR(dB)	70
SFDR(dB)	82
DNL(Max)(+/-LSB)	2
INL(Max)(+/-LSB)	3
No Missing Codes(Bits)	12
ENOB(Bits)	11.3
No. of Supplies	2
Analog Voltage AV/DD(Min)(V)	3.0
Analog Voltage AV/DD(Max)(V)	3.6
Logic Voltage DV/DD(Min)(V)	1.65
Logic Voltage DV/DD(Max)(V)	3.6
Input Configuration Range	2V (p-p)
Reference Mode	Int and Ext
Rating	Catalog
Pin/Package	32QFN
# Input Channels	1
Operating Temperature Range(°C)	-40 to 85

ADS61B23 is a 12-bit A/D converter (ADC) with a maximum sampling frequency of 80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.

ADS61B23 has coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture—controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability.

ADS61B23 特性

Maximum Sample Rate: 80 MSPS
12-bit Resolution with No Missing Codes
Buffered Analog Inputs with
- Very Low Input Capacitance (< 2 pF)
- High DC Resistance (5 kOhm)
82 dBc SFDR and 70 dBFS SNR (-1 BFS or 1.8 Vpp input)
85 dBc SFDR (-6 dBFS or 1 Vpp input)
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR and SFDR Trade-Off
Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
Clock Duty Cycle Stabilizer
Internal Reference with Support for External Reference
External Decoupling Eliminated for References
Programmable Output Clock Position and Drive Strength to Ease Data Capture
3.3 V Analog and 1.8 V to 3.3 V Digital Supply
32-pin QFN Package (5 mm × 5 mm)
Pin Compatible 12-Bit Family (ADS612X)
Temperature range -40°C to 85°C
APPLICATIONS
- Wireless Communications Infrastructure

ADS61B23 芯片订购指南

器件	状态	温度 (oC)	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体
ADS61B23IRHB25	PREVIEW	-40 to 85		QFN (RHB) \| 32	25
ADS61B23IRHBR	ACTIVE	-40 to 85	24.40 \| 100u	QFN (RHB) \| 32	3000 \| LARGE T&R
ADS61B23IRHBRG4	ACTIVE	-40 to 85	24.40 \| 100u	QFN (RHB) \| 32	3000 \| LARGE T&R
ADS61B23IRHBT	ACTIVE	-40 to 85	25.65 \| 100u	QFN (RHB) \| 32	250 \| SMALL T&R
ADS61B23IRHBTG4	ACTIVE	-40 to 85	25.65 \| 100u	QFN (RHB) \| 32	250 \| SMALL T&R