ADS5525 具有 LVDS/CMOS 输出的 12 位 170MSPS ADC

ADS5525 is a high performance 12-bit, 170-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. Using an internal sample and hold and low jitter clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.

In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance.

	ADS5517	ADS5525	ADS5527	ADS5545	ADS5546	ADS5547
Resolution(Bits)	11	12	12	14	14	14
Sample Rate (max)	200MSPS	170MSPS	210MSPS	170MSPS	190MSPS	210MSPS
Architecture	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline
Power Consumption(Typ)(mW)	1230	1100	1230	1100	1130	1230
SINAD(dB)	66	69.8	70.2	73	72.8	72.6
SNR(dB)	66	70.5	70.5	74	73.5	73.3
SFDR(dB)	84	84	84	85	87	85
DNL(Max)(+/-LSB)	0.5	0.5	0.5	0.5	0.5	0.5
INL(Max)(+/-LSB)	2	1	1	3	3	3.5
No Missing Codes(Bits)	11	12	12	14	14	14
ENOB(Bits)	10.8	11.3	11.4	12	11.8	11.8
No. of Supplies	2	2	2	2	2	2
Analog Voltage AV/DD(Min)(V)	3.0	3.0	3.0	3.0	3.0	3.0
Analog Voltage AV/DD(Max)(V)	3.6	3.6	3.6	3.6	3.6	3.6
Logic Voltage DV/DD(Min)(V)	3.6	3.0	3.0	3.0	3.0	3.0
Logic Voltage DV/DD(Max)(V)	3.6	3.6	3.6	3.6	3.6	3.6
Input Configuration Range	2V (p-p)	2V (p-p)	2V (p-p)	2V (p-p)	2V (p-p)	2.2V (p-p)
Reference Mode	Int and Ext	Int and Ext	Int and Ext	Int and Ext	Int and Ext	Int and Ext
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Pin/Package	48VQFN	48VQFN	48VQFN	48VQFN	48VQFN	48VQFN
# Input Channels	1	1	1	1	1	1
Operating Temperature Range(°C)	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85

ADS5525 特性

Maximum Sample Rate: 170 MSPS
12-Bit Resolution
No Missing Codes
Total Power Dissipation 1.1 W
Internal Sample and Hold
70.5-dBFS SNR at 70-MHz IF
84-dBc SFDR at 70-MHz IF
11 bits ENOB Minimum at 70-MHz IF
Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
Reduced Power Modes at Lower Sample Rates
Supports input clock amplitude down to 400 mVPP
Clock Duty Cycle Stabilizer
No External Reference Decoupling Required
Internal and External Reference Support
Programmable Output Clock position to ease data capture
3.3-V Analog and Digital Supply
48-QFN Package (7 mm × 7 mm)
APPLICATIONS
- Wireless Communications Infrastructure

ADS5525 芯片订购指南

器件	状态	温度 (oC)	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体
ADS5525IRGZ25	ACTIVE	-40 to 85	50.00 \| 100u	VQFN (RGZ) \| 48	25
ADS5525IRGZR	ACTIVE	-40 to 85	43.75 \| 100u	VQFN (RGZ) \| 48	2500 \| LARGE T&R
ADS5525IRGZRG4	ACTIVE	-40 to 85	43.75 \| 100u	VQFN (RGZ) \| 48	2500 \| LARGE T&R
ADS5525IRGZT	ACTIVE	-40 to 85	45.00 \| 100u	VQFN (RGZ) \| 48	250 \| SMALL T&R
ADS5525IRGZTG4	ACTIVE	-40 to 85	45.00 \| 100u	VQFN (RGZ) \| 48	250 \| SMALL T&R