PSD834F2V Flash在系统可编程(ISP)的外设对8位微控制器
The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.
Table 1 summarizes all the devices in the PSD834F2, PSD853F2, PSD854F2.
The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/ data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.
The PSD device includes a JTAG Serial Programming interface, to allow In-System Programming (ISP) of the entire device. This feature reduces development time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. Using ST’s special Fast-JTAG programming, a design can be rapidly programmed into the PSD in as little as seven seconds.
The innovative PSD8XXFX family solves key problems faced by designers when managing discrete Flash memory devices, such as:
– First-time In-System Programming (ISP) – Complex address decoding – Simultaneous read and write to the device.
The JTAG Serial Interface block allows In-System Programming (ISP), and eliminates the need for an external Boot EPROM, or an external programmer. To simplify Flash memory updates, program execution is performed from a secondary Flash memory while the primary Flash memory is being updated. This solution avoids the complicated hardware and software overhead necessary to implement IAP.
ST makes available a software development tool, PSDsoft Express, that generates ANSI-C compliant code for use with your target MCU. This code allows you to manipulate the non-volatile memory (NVM) within the PSD. Code examples are also provided for:
- Flash memory IAP via the UART of the host MCU
- Memory paging to execute code across several PSD memory pages
- Loading, reading, and manipulation of PSD macrocells by the MCU.
PSD834F2V 特性:
- FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERAL FOR 8-BIT MCUS
- DUAL BANK FLASH MEMORIES
– UP TO 2 Mbit OF PRIMARY FLASH MEMORY (8 Uniform Sectors, 32K x8)
– UP TO 256 Kbit SECONDARY FLASH MEMORY (4 Uniform Sectors)
– Concurrent operation: READ from one memory while erasing and writing the other - UP TO 256 Kbit of SRAM
- 27 RECONFIGURABLE I/O PORTS
- ENHANCED JTAG SERIAL PORT
- PLD WITH MACROCELLS
– Over 3000 Gates of PLD: CPLD and DPLD
– CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
– DPLD - user defined internal chip select decoding - 27 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
The can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as
open-drain outputs. - IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG
– Built-in JTAG compliant serial port allows full-chip In-System Programmability
– Efficient manufacturing allow easy product testing and programming
– Use low cost FlashLINK cable with PC - PAGE REGISTER
– Internal page register that can be used to expand the microcontroller address space by a factor of 256 - PROGRAMMABLE POWER MANAGEMENT Figure 1. Packages
- HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash Memory
– 1,000 Erase/WRITE Cycles of PLD
– 15 Year Data Retention - 3.3V±10% SINGLE SUPPLY VOLTAGE
- STANDBY CURRENT AS LOW AS 25μA
- Packages are ECOPACK?
PSD834F2V 技术支持与电子电路设计开发资源下载
- PSD834F2V 数据手册DataSheet下载.PDF
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