M48T08 5V,64Kbit(8或× 8)计时器?的SRAM
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE? clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT? READ/WRITE memory cells. The M48T08/18/08Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array.
The M48T08/18/08Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns.
M48T08 订购型号:
| Ordering Model | Package | RoHS Compliance Grade | Marketing Status | Memory Organization | Supply Voltage(Vcc) | Supply Voltage(Vcc) | Operating Range | Packing Type |
| min | max | |||||||
| V | V | |||||||
| M48T08-100PC1 | PDIP 28 .7 ZERO POWER | Ecopack1 | Active | 64Kb (8K x 8) | 4.75 | 5.5 | Commercial | Tube |
| M48T08-150PC1 | PDIP 28 .7 ZERO POWER | Ecopack1 | Active | 64Kb (8K x 8) | 4.75 | 5.5 | Commercial | Tube |
M48T08 产品特性:
- Integrated ultra low power sram, real time clock, power-fail control circuit, and battery
- BYTEWIDE? RAM-like clock access
- BCD coded year, month, day, date, hours, minutes, and seconds
- Typical clock accuracy of ±1 minute a month, at 25°C
- Automatic power-fail chip deselect and write protection
- Write protect
VPFD = Power-fail deselect voltage):
– M48T08: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V
– M48T18/T08Y: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V - Software controlled clock calibration for high accuracy applications
- Self-contained battery and crystal in the CAPHAT? dip package
- Packaging includes a 28-lead SOIC and SNAPHAT? top (to be ordered separately)
- SOIC package provides direct connection for a snaphat top which contains the battery and crystal
- Pin and function compatible with DS1643 and JEDEC standard 8K x8 SRAMs
- RoHS compliant
– Lead-free second level interconnect
M48T08 技术支持与电子电路设计开发资源下载
- M48T08 数据手册DataSheet下载.PDF
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